Post-ECO RTL resynchronization
Less time investigating.
More time engineering.
Ananta is developing tools to help design teams bring RTL back in line with the netlist after engineering change orders, and move toward tapeout with greater confidence.
The problem
After an ECO, the RTL falls behind.
Late engineering changes land in the netlist. Not all of them make it back into the RTL. Finding the ones that did not, and repairing the RTL to match, is manual work that pulls skilled engineers away from building, close to tapeout.
We are building tools to help design teams find those changes and resynchronize the RTL.
Who it’s for
Built for the teams that own the design.
Team 01
RTL design
Engineers who own the RTL.
Team 02
Physical design
Teams who implement changes late in the flow.
Team 03
Design engineering
Other teams carrying a design through to tapeout.
Early development
Early development, and we would like to hear from you.
Ananta is at an early stage. We have not validated it on production designs and we are not claiming results. We are speaking with practitioners to understand where post-ECO resynchronization really hurts.
If that is your world, we would value a short conversation. We are not asking for design data.
We are two engineering students at The University of Texas at Austin, building in Austin, Texas. About the founders.
Or write to mail@anantasilicon.com
Please do not send confidential designs, RTL, netlists or proprietary verification artifacts to this address. We are not asking for them.
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